Error-correction multiplexing apparatus, error-correction demultiplexing apparatus, optical transmission system using them, and error-correction multiplexing transmission method

ABSTRACT

A first demultiplexer and a second demultiplexer receive and demultiplex STM-64 data to generate parallel data. A FEC frame generating encoder carries out error correction encoding operation in a column direction of the parallel data that constitutes a matrix, adds a resulting error correcting code to the parallel data, carries out error correction encoding operation in a row direction of the parallel data, and further adds a resulting error-correcting code to the parallel data. A first multiplexer and a second multiplexer multiplex the error-correction-encoded parallel data, and output the data as a FEC frame.

TECHNICAL FIELD

The present invention relates to an error correction multiplexer, anerror correction demultiplexer, an optical transmission system employingthe error correction multiplexer and the error correction demultiplexer,and a method of error correction multiplexing transmission that correctsbit errors caused by deterioration of signal-to-noise ratio, based onforward error correction (FEC), and to implement long-haul,high-capacity transmission.

BACKGROUND ART

One of the popular optical transmission systems that compensates fordeterioration of the optical signal-to-noise ratio based on forwarderror correction (FEC) is the one recommended by ITU-T G.975. FIG. 22 isa block diagram of an FEC multiplexer at a transmitting end that employsthe FEC method recommended by ITU-T G.975. FIG. 23 is a block diagram ofan FEC demultiplexer at a receiving end that employs the FEC method.

As shown in FIG. 22, a first demultiplexer 211 receives anddemultiplexes an STM-16 data of 2.5 Gbps into 16 parallel data stream of156 Mbps and outputs the 16 parallel data stream to a seconddemultiplexer 212. The second demultiplexer 212 receives and furtherdemultiplexes the 16 parallel data stream into 128 parallel data streamof 19 Mbps, and outputs the 128 parallel data stream to a first rateconverter 213.

The first rate converter 213 receives the 128 parallel data stream of 19Mbps and adds a redundant data area to the data stream. The first rateconverter 213 then rate-converts the 128 parallel data stream of 19 Mbpsinto 128 parallel data stream of 21 Mbps and outputs it to an overheadinserting circuit 214. The overhead inserting circuit 214 inserts anoverhead (OH) bit such as a frame synchronization data that is necessaryfor the maintenance and the operation of the optical system, and outputsthe overhead (OH) data to an encoder 215.

The encoder 215 carries out error correction encoding by means of ReedSolomon (255,239) codes and outputs the encoded data to a firstmultiplexer 216. The first multiplexer 216 multiplexes the 128 paralleldata stream into 16 parallel data stream of 167 Mbps and outputs the 16parallel data stream to a second multiplexer 217. The second multiplexer217 receives the 16 parallel data stream and further multiplexes it to aFEC frame of 2.66 Gbps. The second multiplexer 217 then converts the FECframe of 2.66 Gbps into an optical signal via an optical transmitter andoutputs the optical signal to an optical transmission channel.

The optical signal from the optical transmission channel is convertedinto an electrical signal by an optical receiver and output theelectrical signal to a third demultiplexer 221. The third demultiplexer221 receives and demultiplexes the FEC frame of 2.66 Gbps into 16parallel data stream of 167 Mbps, and outputs the 16 parallel datastream of 167 Mbps to a fourth demultiplexer 222. The fourthdemultiplexing 222 receives the 16 parallel data stream, furtherdemultiplexes it into the 128 parallel data stream of 21 Mbps, andoutputs the 128 parallel data stream of 21 Mbps to a framesynchronization circuit 223.

The frame synchronization circuit 223 detects the header position of theFEC frame based on the frame synchronization data included in anoverhead data area and outputs frame-synchronized data to a decoder 224.The decoder 224 detects and corrects bit errors by means of the ReedSolomon (255,239) codes and outputs the corrected data to an overheadseparating circuit 225.

The overhead separating circuit 225 separates the overhead data area. Asecond rate converter 226 removes the redundant data area in which theerror correction codes are stored, converts the remaining data into the128 parallel data stream of 19 Mbps, and outputs it to a thirdmultiplexer 227. The third multiplexer 227 receives and multiplexes the128 parallel data stream of 19 Mbps to the 16 parallel data stream of156 Mbps, and outputs the 16 parallel data stream of 156 Mbps to afourth multiplexer 228. The fourth multiplexer 228 receives andmultiplexes the 16 parallel data stream of 156 Mbps and outputs it asthe STM-16 data stream of 2.5 Gbps.

The FEC frame is composed of subframes 1 through 128 that include onecolumn of the overhead bit, 238 columns of the STM-16 data, and 16columns of a Reed Solomon (255,239) redundant data. The error correctionencoding is carried out after every eighth subframe.

For instance, in the subframes 1 through 8, the error correctionencoding is carried out for the overhead bit and the STM-16 data, andthe Reed Solomon (255,239) redundant data is stored in columns R0-0through R0-15. As shown in FIG. 24B, the FEC frame is generatedsequentially multiplexing the subframes 1 through 128. If we assume thatthe Reed Solomon (255,239) codes 0 through 15 are multiplexed for ‘f’number of times, then FIG. 24 shows an example when f=16.

The transmission rate in the FEC frame increases 15/14 times withrespect to the original rate of the STM-16. Hence, the transmission rateof the FEC frame becomes 2.66 Gbps. In this way, the bit errors can becorrected by adding the FEC frame and a high quality service can beoffered in an optical transmission system. Hence, an opticaltransmission system that facilitates transmission of high capacity ofsignals over long distances can be built.

When a Reed Solomon (127,111) encoding that has reduced error correctioncodes is carried out on the Reed Solomon (255,239) codes by, forinstance, reducing the STM-16 data of the subframes from 238 columns to110 columns, the percentage of the redundant data corresponding to thedata increases and the error correction capability can be improved.

However, in the optical transmission system described above, when thetransmission distance is increased or the number of wavelengths isincreased using a wavelength multiplexing system, deterioration of thesignal-to noise ratio is considerable. A conventional way to prevent thedeterioration of the signal-to noise ratio is to reduce the errorcorrection codes to improve the constant error correction capability.However, when the error correction codes are reduced, the percentage ofthe redundant data with respect to the data that is supposed to betransmitted increases, resulting in an increase in the transmissionrate. Thus, an optical transmission system that maintains a certainquality and facilitates transmission of high capacity of signals over along distance cannot be built.

For instance, in the Reed Solomon (127,111) encoding, the transmissionrate of the FEC frame becomes 127/111 times to 2.89 Gbps with respect tothe rate of 2.5 Gbps of the STM-16 data, resulting in more deteriorationof the optical transmission characteristics. As a result, even if thecode length is reduced, an optical transmission system that maintains acertain quality and facilitates transmission of high capacity of signalsover a long distance cannot be built.

DISCLOSURE OF THE INVENTION

It is an object of the present invention to solve at least the problemsin the conventional technology.

The error correction multiplexer according to one aspect of the presentinvention includes a demultiplexer that demultiplexes first serial datastream into parallel data stream constituting a matrix, a first encoderthat calculates a first error correcting code from data in a firstdirection of the matrix, and adds the first error correcting code to theparallel data stream, a second encoder that calculates a second errorcorrecting code from data in a second direction of the matrix, and addsthe second error correcting code to the parallel data stream, and amultiplexer that multiplexes the parallel data stream that iserror-correction-coded based on the first error correcting code and thesecond error correcting code into second serial data stream, and outputsthe second serial data stream.

The error correction demultiplexer according to another aspect of thepresent invention includes a demultiplexer that demultiplexes firstserial data stream into first parallel data stream, a decoder thatdecodes the first parallel data stream into third parallel data streambased on the error correcting codes, and a multiplexer that multiplexesthe third parallel data stream into second serial data stream, andoutputs the second serial data stream. The first serial data stream ismultiplexed with a plurality of error correcting codes, and each errorcorrecting code is calculated from data in different direction of amatrix formed by second parallel data stream.

The optical transmission system according to still another aspect of thepresent invention includes a first optical receiver that converts firstoptical signals into electrical signals to generate first serial datastream, an error correction multiplexer, a first optical transmitterthat converts the second serial data stream into second optical signals,an optical transmission line to transmit the second optical signals, asecond optical receiver that converts the second optical signals inputthrough the optical transmission line into electrical signals togenerate third serial data stream, an error correction demultiplexer,and a second optical transmitter that converts the fourth serial datastream into third optical signals. The error correction multiplexerincludes a first demultiplexer that demultiplexes the first serial datastream into first parallel data stream constituting a matrix, a firstencoder that calculates a first error correcting code from data in afirst direction of the matrix, and adds the first error correcting codeto the first parallel data stream, a second encoder that calculates asecond error correcting code from data in a second direction of thematrix, and adds the second error correcting code to the first paralleldata stream, and a first multiplexer that multiplexes the first paralleldata stream that is error-correction-coded based on the first errorcorrecting code and the second error correcting code into second serialdata stream, and outputs the second serial data stream. The errorcorrection demultiplexer includes a second demultiplexer thatdemultiplexes the third serial data stream into second parallel datastream, a decoder that decodes the second parallel data stream intothird parallel data stream based on the error correcting codes, and asecond multiplexer that multiplexes the third parallel data stream intofourth serial data stream, and outputs the fourth serial data stream;and

The method of error correction multiplexing transmission according tostill another aspect of the present invention includes demultiplexingfirst serial data stream into first parallel data stream constituting amatrix, calculating a first error correcting code from data in a firstdirection of the matrix, adding the first error correcting code to thefirst parallel data stream, calculating a second error correcting codefrom data in a second direction of the matrix, adding the second errorcorrecting code to the first parallel data stream, and multiplexing thefirst parallel data stream into second serial data stream.

The other objects, features and advantages of the present invention arespecifically set forth in or will become apparent from the followingdetailed descriptions of the invention when read in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an optical transmission system according toa first embodiment of the present invention;

FIG. 2 is a block diagram of the FEC multiplexer shown in FIG. 1;

FIG. 3 is a block diagram of the FEC demultiplexer shown in FIG. 1;

FIG. 4( a) and (b) illustrate a process of error correction encoding bymeans of the FEC multiplexer shown in FIG. 2;

FIG. 5 is a detailed block diagram of the FEC multiplexer shown in FIG.1;

FIG. 6 is a detailed block diagram of the FEC demultiplexer shown inFIG. 1;

FIG. 7 is a block diagram of an optical transmission system according toa second embodiment of the present invention;

FIG. 8 is a block diagram of the FEC demultiplexer shown in FIG. 7;

FIG. 9 is a detailed block diagram of the FEC demultiplexer shown inFIG. 7;

FIG. 10 is a block diagram of a FEC multiplexer of an opticaltransmission system according to a third embodiment of the presentinvention;

FIG. 11 is a block diagram of a FEC demultiplexer of the opticaltransmission system according to the third embodiment of the presentinvention;

FIG. 12 is a detailed block diagram of the FEC multiplexer shown in FIG.10;

FIG. 13 is a block diagram of the FEC demultiplexer shown in FIG. 11;

FIG. 14 is a block diagram of an optical transmission system accordingto a fourth embodiment of the present invention;

FIG. 15 is a block diagram FEC demultiplexer shown in FIG. 14;

FIG. 16 is a detailed block diagram of the specific detailed structureof the FEC demultiplexer shown in FIG. 14;

FIG. 17 is a block diagram of a FEC multiplexer of an opticaltransmission system according to a sixth embodiment of the presentinvention;

FIG. 18 is a block diagram of a FEC demultiplexer of the opticaltransmission system according to the sixth embodiment of the presentinvention;

FIG. 19( a) and (b) illustrate a process of error correction encoding bymeans of the FEC multiplexer shown in FIG. 17;

FIG. 20 illustrates an example of the process of error correctionencoding carried out with respect to a multiframe by means of the FECmultiplexer shown in FIG. 18;

FIG. 21 is a block diagram that illustrates an example of an outlinestructure of a process of error correction encoding in a FEC multiplexeraccording to a seventh embodiment of the present invention;

FIG. 22 is a block diagram of a FEC multiplexer according to aconventional optical transmission system;

FIG. 23 is a block diagram of a FEC demultiplexer according to theconventional optical transmission system; and

FIG. 24A and FIG. 24B illustrate a frame structure of a FEC frame.

BEST MODE FOR CARRYING OUT THE INVENTION

An error correction multiplexer, an error correction demultiplexer, anoptical transmission system employing the error correction multiplexerand demultiplexer, and a method of error correction multiplexingtransmission are explained in detail with reference to the accompanyingdrawings.

FIG. 1 is a block diagram of the optical transmission system accordingto a first embodiment of the present invention. In this opticaltransmission system, a first optical receiver 1 receives a STM-64optical signal, converts the optical signal into an electrical signal,and outputs the electrical signal to a FEC multiplexer 2.

The FEC multiplexer 2 multiplexes the electrical signal received fromthe first optical receiver 1, inserts an overhead (OH) bit, calculatesand generates error-correcting codes, etc., multiplexes theerror-correcting codes, creates a FEC frame that includes themultiplexed error-correcting codes, and outputs the FEC frame to a firstoptical transmitter 3. The first optical transmitter 3 converts theelectric signal of the FEC frame received from the FEC multiplexer 2into an optical signal and outputs this optical signal to an opticaltransmission channel 4 that comprises optical fibers.

A second optical receiver 5 receives the optical signal from the opticaltransmission channel 4, converts the optical signal to an electricalsignal, and outputs the electrical signal to a FEC demultiplexer 6. TheFEC demultiplexer 6 receives the FEC frame, determines the framesynchronization of the FEC frame, decodes the error-correcting codesbased on the added error-correcting codes, separates the added overheadbit, again multiplexes the electrical signal, and outputs themultiplexed electrical signal to a second optical receiver 7. The secondoptical receiver 7 receives and converts the electrical signal into anoptical signal, and outputs the converted optical signal as the STM-64optical signal.

Transmitting a large amount of optical signals over long distances maygive rise to deterioration of signal-to-noise ratio in the opticaltransmission channel 4 and cause numerous bit errors in the FEC frameoutput from the second optical receiver 5. These bit errors arecorrected by the FEC demultiplexer 6. Consequently, the bit error rateof the STM-64 optical signal can be considerably improved and atransmission service of a prescribed quality can be maintained.

FIG. 2 is a block diagram of the FEC multiplexer 2 shown in FIG. 1. Afirst demultiplexer 11 receives the STM-64 (of 9.95 Gbps) electricalsignal, which is a serial data stream, from the first optical receiver1, demultiplexes the serial data stream into n parallel datastream(where n is positive integer), and outputs the n parallel datastream to a second demultiplexer 12.

The second demultiplexer 12 receives the n parallel data stream,demultiplexes them into (n×(m−i)) parallel data stream (where m and iare positive integers and m is greater than i), and outputs the(n×(m−i)) parallel data stream to a FEC frame generating encoder 13.

The FEC frame generating encoder 13 receives the (n×(m−i)) parallel datastream, creates (n×m) parallel data stream by storing the overhead bit,creating a redundant data area, and storing in the redundant data areathe error-correcting codes generated by error correction encoding. TheFEC frame generating encoder then outputs the (n×m) parallel data streamto a first multiplexer 14.

The first multiplexer 14 receives the (n×m) parallel data stream,multiplexes them into n parallel data stream, and outputs the n paralleldata stream to a second multiplexer 15. The second multiplexer 15receives the n parallel data stream, multiplexes and converts it into aserial data stream, and outputs this serial data stream as a FEC frameto the first optical transmitter 3.

FIG. 3 is a block diagram of the FEC demultiplexer 6 shown in FIG. 1. Athird demultiplexer 21 receives the FEC frame from the second opticaltransmitter 5, demultiplexes it into n parallel data stream, and outputsthe n parallel data stream to a fourth demultiplexer 22. The fourthdemultiplexer 22 receives the n parallel data stream, demultiplexes then parallel data stream into (n×m) parallel data stream, and outputs the(n×m) parallel data stream to a FEC frame bottom decoder 23.

The FEC frame bottom decoder 23 receives the (n×m) parallel data streamfrom the fourth demultiplexer 22, determines the frame synchronization,carries out processes such as overhead bit extraction, error decodingbased on error encoding, etc., finally creates (n×(m−i)) parallel datastream, and outputs the (n×(m−i)) parallel data stream to a thirdmultiplexer 24. The third multiplexer 24 receives the (n×(m−i)) paralleldata stream, multiplexes and converts it into n parallel data stream,andoutputs it to a fourth multiplexer 25. The fourth multiplexer 25receives the n parallel data stream, multiplexes and converts it into aserial data stream, and outputs the serial data stream as a STM-64serial data stream (electrical signal) to the second optical receiver 7.

FIG. 4( a) and (b) are schematic diagrams that illustrate the errorcorrection encoding process of the FEC frame generating encoder 13 shownin FIG. 2. The STM-64 data is stored in a data area E1. An overhead dataarea E2 is disposed in the column before the data area E1. Overheadinformation related to maintenance and operation of the network, ofwhich the optical transmission system is a part, is stored in theoverhead data area E2. A fixed stuff area E3 is provided for absorbingthe difference between code length of the (n×(m−i)) parallel data streamand the code length n1 in the direction of the column. The data area E1,the overhead data area 2, and the fixed stuff area E3 form a matrix ofk2×k1.

An error-correcting code in the column direction and having a codelength n1, a data length k1, and a redundant bit length r1, is placed inthe row direction k2 in a redundant data area E5 (FIG. 4( a)). Followingthe placing of the error-correcting code in the redundant data area E5,an error-correcting code in the row direction and having a code lengthn2, a data length k2, and a redundant bit length r2, is placed in thecolumn direction n1. in redundant data area E4 (FIG. 4( b)). As n×m=n1,the width fs1 of the fixed stuff area E3 in the column direction isdetermined by the expression fs1=n×i−r1, where n1, n2, k1, k2, r1, r2,and fs1 are all positive integers.

In other words, the error-correcting codes placed in the redundant dataareas E4 and E5 are processed in directions that are mutually orthogonaland each error-correcting code is independent of the other. As a result,an error correction in the column direction can be carried out using theerror correction result in the row direction. Similarly, an errorcorrection in the row direction can be carried out using the errorcorrection result in the column direction. In this way, a superior errorcorrection capability can be achieved.

The structures of the FEC multiplexer 2 and the FEC demultiplexer 6 areexplained in detail next. FIG. 5 is a detailed block diagram of the FECmultiplexer 2 shown in FIG. 1. FIG. 6 is a detailed block diagram of theFEC demultiplexer 6 shown in FIG. 1. Here, the error-correcting codesstored in the redundant data areas E4 and E5 are BCH signals of valuesBCH(128,113). Consequently, n1=n2=128, k1=k2=113, r1=r2=15, and fs1=1.

In FIG. 5, a first 1 to 16 serial-parallel converter 31 demultiplexes aSTM-64 serial data stream (of 9.95 Gbps) into 16 parallel data stream of622 Mbps and outputs each 16 parallel data stream to a corresponding 1to 7 serial-parallel converter 32 placed next. There are sixteen 1 to 7serial-parallel converters 32 arranged in a parallel fashion. Each ofthe sixteen 1 to 7 serial-parallel converters 32 demultiplexes thereceived 16 parallel data stream into 7 parallel data stream,collectively generates 112 parallel data stream of 89 Mbps, and outputsthe 112 parallel data stream to a first rate converter 33.

The first rate converter 33 receives the 112 parallel data stream of 89Mbps, adds to the 112 parallel data stream the overhead data area E2 andthe redundant data area E4, and outputs the 112 parallel data stream toa overhead inserting circuit 34 as 112 parallel data stream of 102 Mbps.The overhead inserting circuit 34 inserts in the overhead data area E2overhead bit such as frame synchronization data, etc., required for themaintenance and operation of the optical transmitting system and outputsthe 112 parallel data stream to an encoder 35.

The encoder 35 includes a first encoder 35 a and a second encoder 35 b.The first encoder 35 a receives the 112 parallel data stream, calculatesthe error-correcting code for the column direction in the entire rowdirection k2 of 113 parallel data stream, which is obtained by adding tothe 112 parallel data stream the fixed stuff area E3 (which has a widthfs1 of one line in the column direction) in which dummy bits are stored.The first encoder 35 a then adds the redundant data area E5 to the 113parallel data stream and stores the error-correcting code in theredundant data-area E5. The second encoder 35 b calculates theerror-correcting code for the row direction in the width r1=15 in therow direction of the redundant data area E5. In other words, the secondencoder 35 b calculates the error-correcting code in the row directionof the 128 parallel data stream which has been increased by 15. Thesecond encoder 35 b then stores the error-correcting code in theredundant data area E4. Following this, the encoder 35 splits the 128parallel data stream into 16 and outputs each of the 16 parallel datastream to a corresponding 8 to 1 parallel-serial converter 36 placednext. There are sixteen 8 to 1 parallel-serial converters 36 arranged ina parallel fashion.

Each 8 to 1 parallel-serial converter 36 multiplexes the received 128parallel data stream of 102 Mbps. The multiplexed 128 parallel datastream of 102 Mbps output from each of the sixteen 8 to 1parallel-serial converter are collectively output as 16 parallel datastream of 812 Mbps to a first 16 to 1 parallel-serial converter 37placed next. The first 16 to 1 parallel-serial converter 37 multiplexesand converts the received 16 parallel data stream into a FEC frame,which is a serial data stream of 13 Gbps and outputs the serial datastream to the first optical transmitter 3.

The functioning of the FEC multiplexer shown in FIG. 5 is explainednext. The 112 parallel data stream of 89 Mbps output from the sixteenparallel 1 to 7 serial-parallel converters 32 is data that is stored inthe data area E1. To this 112 parallel data stream, the overhead dataarea E2 and the redundant data area E4 are added by the first rateconverter 33 following which the data becomes 112 parallel data streamof 102 Mbps. After the overhead bits are stored in the overhead dataarea E2 of this 112 parallel data stream, the encoder 35 carries outBCH(128,113) encoding for the column direction of the 113 parallel datastream, which is obtained by forming the fixed stuff area E3 of widthfs1 of one line in the column direction) to which dummy data is added inorder to align the code length. The encoder 35 then adds the redundantdata area E5, stores the error-correcting code in the redundant dataarea E5, and creates 128 parallel data stream. Following this, theencoder 35 carries out BCH(128,113) encoding in the row direction, andstores the error-correcting code in the redundant data area E4, creating128 parallel data stream of 102 Mbps.

The transmission rate of the final FEC frame of a STM-64 data of 9.95Gbps increases to 13 Gbps due to the addition of the redundant dataareas E4 and E5 and the resultant 128/112)×(128/112)-times increase inthe row direction and the column direction.

Consequently, the FEC multiplexer creates a FEC frame with k2 BCH codescalculated in the column direction and n1 BCH codes calculated in therow direction. As a result, the error correction capability of the FECmultiplexer can be considerably enhanced. Further, the seconddemultiplexer 12 shown in FIG. 2 comprises sixteen 1 to 7serial-parallel converters 32 arranged in a parallel fashion and addsthe redundant data area E4 to the data stream. Consequently, theredundant data area E4 is easily added even to a high rate data, therebysimplifying the overall circuitry.

In FIG. 6, a second 1 to 16 serial-parallel converter 41 receives theFEC frame from the second optical receiver 5 and demultiplexes the FECframe of 13 Gbps into 16 parallel data stream of 812 Mbps. Each of the16 parallel data stream is split into 16. Each of the 16 data stream isoutput to a corresponding 1 to 8 serial-parallel converter 42 placednext. There are sixteen 1 to 8 serial-parallel converters 42 arranged ina parallel fashion. Each 1 to 8 serial-parallel converter 42 furtherdemultiplexes the received data stream into 8 parallel data stream,collectively generates 128 parallel data stream of 102 Mbps, and outputsthe 128 parallel data stream to a frame synchronization circuit 43.

The frame synchronization circuit 43 checks the frame synchronizationpattern from the overhead data area E2 of the received 128 parallel datastream, detects the header position of the frame created by the received128 parallel data stream, and outputs a frame-synchronized 128 paralleldata stream to a decoder 44. The decoder 44 includes a first decoder 44a and a second decoder 44 b. The first decoder 44 a carries out errorcorrection in the row direction based on the error-correcting codestored in the redundant data area E4. The second decoder 44 b carriesout error correction in the column direction based on theerror-correcting code stored in the redundant data area E5, and outputsto an overhead separating circuit 45 112 parallel data stream of 102Mbps from which the redundant data area E5 has been removed. Theoverhead separating circuit 45 removes the overhead bit stored in theoverhead data area E2 and outputs to a second rate converter 46 the 112parallel data stream of 102 Mbps from which the overhead bit has beenremoved.

The second rate converter 46 removes the overhead data area E2 and theredundant data area E4 from the received 112 parallel data stream andconverts it into 112 parallel data stream of 89 Mbps. The second rateconverter 46 then outputs the 112 parallel data stream as 7 paralleldata stream to each of sixteen 7 to 1 parallel-serial converters 47arranged next in a parallel fashion. Each of the sixteen 7 to 1parallel-serial converters 47 then multiplexes the received 7 paralleldata stream, collectively generates 16 parallel data stream of 622 Mbps,and outputs the 16 parallel data stream to a second 16 to 1parallel-serial converter 48. The second 16 to 1 parallel-serialconverter 48 multiplexes and converts the received 16 parallel datastream into a STM-64 data of 9.95 Gbps and outputs the STM-64 data tothe second optical receiver 7.

The functioning of the FEC demultiplexer 6 is explained next. Based onthe error-correcting code in the row direction stored in the redundantdata area E4, the first decoder 44 a decodes each row of the 128parallel data stream of 102 Mbps and corrects the bit error. However,when the bit errors exceed the error correction capability, some biterrors remain uncorrected. Here, the second decoder 44 b also corrects,based on the error-correcting code in the column direction stored in theredundant data area E5, the bit errors remaining in the row direction.Consequently, as the bit errors are distributed between the rowdirectional error-correcting code and the column directionalerror-correcting code of the FEC frame, a superior error correctioncapability can be achieved.

In the encoder 35, error correction encoding in the column direction andthe row direction can be achieved by providing an interleaver betweenthe first encoder 35 a and the second encoder 35 b.

The interleaver can be implemented by means of an X-Y convertingcircuit. The interleaver in the first embodiment of the presentinvention is included in the second encoder 35 b. Similarly, in thedecoder 44 as well, error correction encoding in the column directionand the row direction can be achieved by providing an interleaverbetween the first decoder 44 a and the second decoder 44 b, and adeinterleaver at the output end of the second decoder 44 b. Again, boththe interleaver and the deinterleaver are implemented by means of an X-Yconverting circuit. The interleaver and the deinterleaver in the firstembodiment of the present invention are included in the second decoder44 b.

In the first embodiment of the present invention, during the errorcorrection encoding, the error correction encoding in the row directionfollows the error correction encoding in the column direction, andduring error correction decoding, the error correction decoding in thecolumn direction follows the error correction decoding in the rowdirection. However, this is not a hard and fast rule and the sequence oferror correction encoding and decoding may be reversed. That is, duringthe error correction encoding, the error correction encoding in the rowdirection may be carried out before the error correction encoding in thecolumn direction. Similarly, during the error correction decoding, theerror correction decoding in the column direction may be carried outbefore the error correction decoding in the row direction. In short,when creating the FEC frame, a two-stage error correction encoding and atwo-stage error correction decoding in directions that are mutuallyorthogonal may be carried out so that bit errors may be distributedbetween the error-correcting codes.

Further, in the first embodiment of the present invention, during theerror correction encoding in the row direction, error correctionencoding for the error-correcting code in the column direction, forwhich the error correction encoding has been done once, is carried outagain. This again is not a hard and fast rule. That is, during the errorcorrection encoding in the column direction, the error correctionencoding for the error-correcting code in the row direction, for whicherror correction encoding has been done once, may be carried out again.However, error correction in the row direction occurs when errorcorrection encoding in the row direction is carried out while errorcorrection encoding in the column direction is taking place. As aresult, the error correction encoding of a higher accuracy can becarried out.

According to the first embodiment of the present invention, theredundant data area E4, in which the error-correcting code obtained byerror correction encoding in the row direction of (n×(m−i)) paralleldata stream are stored, is added by the second demultiplexer 12.Besides, the (n×(m−i)) parallel data stream is multiplexed into nparallel data stream by the third multiplexer 24. Fast conversiontherefore is achieved with such a simple structure. In addition, in thepresent embodiment, a superior error correction capability is achievedas the bit errors that remain uncorrected following a first errorcorrection are reliably corrected. Hence, an optical transmission systemwith enhanced error correction capability and in which transmission of alarge amount of signals over long distances can be achieved.

Second Embodiment

A second embodiment of the present invention is explained next. In thesecond embodiment, a soft decision decoding process has been implementedon the device at the receiver (decoding) end.

FIG. 7 illustrates the overall structure of the optical transmissionsystem according to the second embodiment of the present invention. Thisoptical transmission system includes, instead of the second opticalreceiver 5 and the FEC demultiplexer 6 of the optical transmissionsystem shown in FIG. 1, a second optical receiver 55 and a FECdemultiplexer 56, respectively. The rest of the structure shown in FIG.1 and FIG. 7 is identical and identical parts in the two drawings areassigned identical reference numerals. The second optical receiver 55,as well as converting optical signals received from an opticaltransmission channel 4 into electrical signals, carries out a softdecision process on the electrical signals, quantizes the binary datainto j bits (where j is a positive integer of 2 or greater), and outputsa FEC frame as 3 parallel data stream of 13 Gbps to the FECdemultiplexer 56. The FEC demultiplexer 56 carries out a soft decisiondecoding based on the 3 parallel data stream.

FIG. 8 is a detailed block diagram of the FEC demultiplexer 56 shown inFIG. 7. The FEC demultiplexer 56 includes, instead of the thirddemultiplexer 21, the fourth demultiplexer 22, and the FEC frame bottomdecoder 23 of the FEC demultiplexer 6 shown in FIG. 3, a thirddemultiplexer 51, a fourth demultiplexer 52, and a FEC frame bottomdecoder 53, respectively. The rest of the structure shown in FIG. 3 andFIG. 8 is identical and identical parts in the two drawings are assignedidentical reference numerals.

In FIG. 8, the third demultiplexer 51 demultiplexes the j parallel datastream of 13 Gbps output from the second optical receiver 55 into (n×j)parallel data stream and outputs the (n×j) parallel data stream to thefourth demultiplexer 52. The fourth demultiplexer 52 demultiplexes thereceived (n×j) parallel data stream into (n×m×j) parallel data streamand outputs the (n×m×j) parallel data stream to the FEC frame bottomdecoder 53. The FEC frame bottom decoder 53 carries out a soft decisiondecoding process based on the received (n×m×j) parallel data stream andoutputs a decoded (n×(m−i)) parallel data stream.

The FEC demultiplexer 56 shown in FIG. 8 is explained next withreference to the detailed block diagram shown in FIG. 9. The FECdemultiplexer 56 includes, instead of the second 1 to 16 serial-parallelconverter 41, the 1 to 8 serial-parallel converter 42, and the encoder44 of the FEC multiplexer shown in FIG. 6, a (1 to 16)×3 serial-parallelconverter 61, a (1 to 8)×3 serial-parallel converter 62, and an encoder64, respectively. The rest of the structure in FIG. 6 and FIG. 9 isidentical and identical parts in the two drawings are assigned identicalreference numerals.

The (1 to 16)×3 serial-parallel converter 61 demultiplexes the received3 parallel data stream of 812 Mbps into 48 (16×3) parallel data streamof 812 Mbps, splits this 48 parallel data stream into 3 streams, andoutputs each of the 3 parallel data stream to a corresponding (1 to 8)×3serial-parallel converter 62 placed next. There are sixteen (1 to 8)×3serial-parallel converters 62 arranged in a parallel fashion. Each (1 to8)×3 serial-parallel converter 62 demultiplexes the 24 ((8×3)) paralleldata stream, collectively generates a 348 ((128×3)), and outputs the 384parallel data stream of 102 Mbps to a frame synchronization circuit 43.The frame synchronization circuit 43 checks the frame synchronizationpattern from the overhead bit, detects the header position of the frameof the FEC frame, and outputs the frame-synchronized 384 parallel datastream to the decoder 64.

The decoder 64 carries out the soft decision decoding of the 384parallel data stream of 102 Mbps as 3 quantized 128 parallel datastream, and outputs a decoded 112 parallel data stream to a overheadseparating circuit 45. The subsequent steps are the same as those in thefirst embodiment.

The decoder 64 comprises a first decoder 64 a, which corresponds to thefirst decoder 44 a, and a second decoder 64 b, which corresponds to thesecond decoder 44 b. The first decoder 64 a decodes the error-correctingcode in the row direction and, as a result, outputs a 3 soft decisionvalue. The second decoder 64 b outputs decodes the error-correcting codein the column direction and, as a result, outputs a 3 soft decisionvalue. The second decoder 64 b then outputs, based on this soft decisionvalue, the final decoding result.

In general, error correction capability improves remarkably with a softdecision decoding as compared to a hard decision decoding. Consequently,by employing a soft decision decoding, an optical transmission systemcan be achieved which can transmit a large amount of signals over longdistances. A structure may be such that the frame synchronizationcircuit 43 may determine frame synchronization either by a 3 softdecision data or by a hard decision data.

To sum up, according the second embodiment, the third demultiplexer 51demultiplexes the j parallel data stream, which is quantized into j bitsby the soft decision process, into the (n×j) parallel data stream. Thefourth demultiplexer 52 demultiplexes the (n×j) parallel data streaminto the (n×m×j) parallel data stream and converts the j data quantizedthe soft decision process into a low rate (n×m×j) parallel data stream.The FEC frame bottom decoder 53 then carries out the error correctiondecoding. In this way, with a simple structure signals can betransmitted at a high rate. Further, the error correction capability ofsuch a structure is considerably improved with enhanced transmissionrate of a large amount of signals over long distances.

A third embodiment of the present invention is explained next. Thegeneral structure of the optical transmission system according to thethird embodiment is identical to that of the first embodiment. However,the structure and functionality of a FEC multiplexer 2 and a FECdemultiplexer 6 in the third embodiment are different from those in thefirst embodiment.

FIG. 10 is a block diagram of the FEC multiplexer 2 according to thethird embodiment. A first demultiplexer 71 demultiplexes serial datastream which are electrical signals of STM-64 (9.95 Gbps) received froma first optical receiver and outputs the serial data stream as n (wheren is a positive integer) parallel data stream to a second demultiplexer72.

The second demultiplexer 72 demultiplexes the received n parallel datastream into (n×m) (where m is a positive integer) parallel data streamand outputs the (n×m) (where m is a positive integer) parallel datastream to a FEC frame generating encoder 73.

The FEC frame generating encoder 73 stores in the received (n×m)parallel data stream an overhead bit, creates a (n×(m+i)) (where m and iare positive integers and m is greater than i) parallel data streamobtained after storing in the redundant data area the error-correctingcodes created by error correction encoding, and outputs the (n×(m+i))parallel data stream to a first multiplexer 74.

The first multiplexer 74 multiplexes the received (n×(m+i)) paralleldata stream into n parallel data stream and outputs the n parallel datastream to a second multiplexer 75. The second multiplexer 75 multiplexesand converts the n parallel data stream into a serial data stream, andoutputs the serial data stream to a first optical transmitter 3.

FIG. 11 is a block diagram of the FEC demultiplexer 6 according to thethird embodiment. A third demultiplexer 81 demultiplexes a FEC framereceived from a second optical receiver and outputs as n parallel datastream to a fourth demultiplexer 82. The fourth demultiplexer 82demultiplexes the received n parallel data stream into (n×(m+1))parallel data stream and outputs the (n×(m+1)) parallel data stream to aFEC frame bottom decoder 83.

The FEC frame bottom decoder 83 determines the frame synchronization ofthe (n×(m+1)) parallel data stream received from the fourthdemultiplexer 82, carries out error correction decoding based on theextracted overhead bit and the error-correcting codes, finally creates(n×m) parallel data stream, and outputs the (n×m) parallel data streamto a third multiplexer 84. The third multiplexer 84 multiplexes thereceived (n×m) parallel data stream into n parallel data stream andoutputs the n parallel data stream to a fourth multiplexer 85. Thefourth multiplexer 85 converts the n parallel data stream received fromthe third multiplexer 84 into a serial data stream and outputs theserial data stream (electrical signals) as a STM-64 (9.95 Gbps) to asecond optical receiver 7.

The FEC frame generating encoder 73 carries out the error correctionencoding according to FIG. 4 except that, in this case n1=n×(m+1). As inthe first embodiment, in the third embodiment also the error-correctingcodes placed in the redundant data areas E4 and E5 are processed indirections that are mutually orthogonal and each error-correcting codeis independent of the other error-correcting code. As a result, an errorcorrection in the column direction can be carried out using the errorcorrection result in the row direction. Similarly, an error correctionin the row direction can be carried out by using the error correctionresult in the column direction. In this way, the error correctioncapability can be considerably improved.

The FEC multiplexer 2 and the FEC demultiplexer 6 according to the thirdembodiment of the present invention are explained in detail next. FIG.12 is a detailed block diagram of the FEC multiplexer shown in FIG. 10.FIG. 13 is a detailed block diagram of the FEC demultiplexer shown inFIG. 11. The error-correcting codes stored in the redundant data areasE4 and E5 are different BCH codes. The error-correcting code in theredundant data area E4 is a BCH(144,128) code and that in the redundantdata area E5 is a BCH(256,239). In other words, n1=144, n=256, k1=128,k2=239, r1=16, r2=17, and fs1=0.

In FIG. 12, a first 1 to 18 serial-parallel converter 91 demultiplexes aserial data stream of STM-64 (9.95 Gbps), creates 16 parallel datastream of 622 Mbps, and outputs each 16 parallel data stream to acorresponding 1 to 8 serial-parallel converter 92 placed next. There aresixteen 1 to 8 serial-parallel converters 92 arranged in a parallelfashion. Each of the 16-parallel 1 to 8 serial-parallel converters 92demultiplexes the received 16 parallel data stream into 8 parallel datastream, collectively generates 128 parallel data stream of 78 Mbps, andoutputs the 128 parallel data stream to a first rate converter 93.

The first rate converter 93 adds the overhead data area E2 and theredundant data area E4 to the received 128 parallel data stream of 78Mbps and outputs the 128 parallel data stream of 84 Mbps to an overheadinserting circuit 94. The overhead inserting circuit 94 inserts in theoverhead data area E2 overhead bit such as frame synchronization data,etc., required for the maintenance and operation of the opticaltransmitting system and outputs the 128 parallel data stream to anencoder 95.

The encoder 95 includes a first encoder 95 a and a second encoder 95 b.The first encoder 95 a receives the 128 parallel data stream, calculatesthe error-correcting code in the column direction. The first encoder 95a then adds the redundant data area E5 to the 128 parallel data streamand stores the error correcting code in the redundant data area E5. Theredundant data area E5 increases by the width r1 in the columndirection, that is by 16. The second encoder 95 b calculates theerror-correcting code in the row direction of the 16-added 144 paralleldata stream and stores the error-correcting code in the redundant dataarea E4. Following this, the encoder 95 splits the 144 parallel datastream into 16 and outputs each of the 16 parallel data stream to acorresponding 9 to 1 parallel-serial converter 96. There are sixteen 9to 1 parallel-serial converters 96 arranged in a parallel fashion.

Each 9 to 1 parallel-serial converter 96 multiplexes the received 144parallel data stream of 84 Mbps. The multiplexed 14 parallel data streamof 96 Mbps output from each of the sixteen 9 to 1 parallel-serialconverter are collectively output as 16 parallel data stream of 753 Mbpsto a first 16 to 1 parallel-serial converter 97 placed next. The first16 to 1 parallel-serial converter 97 multiplexes and converts thereceived 16 parallel data stream into a FEC frame, which is a serialdata stream of Gbps and outputs the serial data stream to the firstoptical transmitter 3.

The function of the FEC multiplexer shown in FIG. 12 is explained next.The 128 parallel data stream of 78 Mbps output from the sixteen parallel1 to 7 serial-parallel converters 92 is data that is stored in the dataarea E1. To this 128 parallel data stream, the overhead data area E2 andthe redundant data area E4 are added by the first rate converter 93following which the data becomes 128 parallel data stream of 84 Mbps.After the overhead bits are stored in the overhead data area E2 of this128 parallel data stream, the encoder 95 carries out BCH(144,128)encoding for the column direction of the 128 parallel data stream. Theencoder 95 then adds the redundant data area E5, stores theerror-correcting code in the redundant data area E5, and creates 144parallel data stream. Following this, the encoder 95 carries outBCH(256,239) encoding for the column direction, stores theerror-correcting code in the redundant data area E4, creating 144parallel data stream of 84 Mbps.

The transmission rate of the final FEC frame of a STM-64 data of 9.95Gbps increases to 12 Gbps due to addition of the redundant data areas E4and E5 and the resultant (144/128)×(256/238)-times increase in the rowdirection and the column direction.

Thus, by creating a frame of BCH(144,128), which are theerror-correcting code in the column direction n2, and BCH(256,238),which are the error-correcting code in the row direction n1, the errorsoccurring in an optical transmission channel 4 are distributed,resulting in a superior error correction capability. Further the seconddemultiplexer 72 comprises sixteen 1 to 8 serial-parallel converters 92arranged in a parallel fashion and adds the redundant data area E4 tothe data stream. Consequently, the redundant data area E4 is easilyadded even to high rate data, thereby simplifying the overall circuitry.

In FIG. 13, a second 1 to 16 serial-parallel converter 101 receives theFEC frame from a second optical receiver 5 and demultiplexes the FECframe of 12 Gbps into 16 parallel data stream of 753 Mbps. Each of the16 parallel data stream is split into sixteen. Each of the sixteen datastream is output to a corresponding 1 to 9 serial-parallel converter 102placed next. There are sixteen 1 to 9 serial-parallel converters 102arranged in a parallel fashion. Each 1 to 9 serial-parallel converter102 further demultiplexes the received data stream into 9 parallel datastream, collectively generates 144 parallel data stream of 84 Mbps, andoutputs the 144 parallel data stream to a frame synchronization circuit103.

The frame synchronization circuit 103 checks the frame synchronizationpattern from the overhead data area E2 of the received 144 parallel datastream, detects the header position of the frame created by the received144 parallel data stream, and outputs a frame-synchronized 128 paralleldata stream to a decoder 104. The decoder includes a first decoder 104 aand a second decoder 104 b. The first decoder 104 a carries out errorcorrection in the row direction based on the error-correcting codestored in the redundant data area E4. The second decoder 104 b carriesout error correction in the column direction based on theerror-correcting code stored in the redundant data area E5 and outputsto an overhead separating circuit 105 128 parallel data stream of 84Mbps from which the redundant data area E5 has been removed. Theoverhead separating circuit 105 removes the overhead bit stored in theoverhead data area E2 and outputs to a second rate converter 106 the 128parallel data stream of 78 Mbps from which the overhead bit has beenremoved.

The second rate converter 106 removes the overhead data area E2 and theredundant data area E4 from the received 128 parallel data stream andconverts it into a 128 parallel data stream of 78 Mbps. The second rateconverter 106 then outputs the 128 parallel data stream as 8 paralleldata stream to each of sixteen 8 to 1 parallel-serial converters 107arranged next in a parallel fashion. Each of the sixteen 8 to 1parallel-serial converters 107 then multiplexes the received 8 paralleldata stream, collectively generates 16 parallel data stream of 622 Mbps,and outputs the 16 parallel data stream to a second 16 to 1parallel-serial converter 108. The second 16 to 1 parallel-serialconverter 108 multiplexes and converts the received 16 parallel datastream into a STM-64 data of 9.95 Gbps and outputs the STM-64 data to asecond optical receiver 7.

The functioning of the FEC demultiplexer is explained next. Based on theerror-correcting code in the row direction stored in the redundant dataarea E4, the first decoder 104 a decodes each row of the 128 paralleldata stream of 84 Mbps and corrects the bit error. However, when the biterror exceeds the error correction capability, some of the bit errorsremain uncorrected. Here, the second decoder 104 b also corrects, basedon the error-correcting code in the column direction stored in theredundant data area E5, the bit errors remaining in the row direction.Consequently, as the bit errors are distributed between the rowdirectional error-correcting code and the column directionalerror-correcting codes of the FEC frame, a superior error correctioncapability can be achieved.

In the encoder 95, error correction encoding in the column direction andthe row direction can be achieved by providing an interleaver betweenthe first encoder 95 a and the second encoder 95 b. The interleaver canbe implemented by means of an X-Y converting circuit. The interleaver inthe third embodiment of the present invention is included in the secondencoder 95 b. Similarly, in the decoder 104 as well, error correctionencoding in the column direction and the row direction can be achievedby proving an interleaver between the first decoder 104 a and the seconddecoder 104 b, and a deinterleaver at the output end of the seconddecoder 104 b. Again, both the interleaver and the deinterleaver areimplemented by means of an X-Y converting circuit. The interleaver andthe deinterleaver in the third embodiment of the present invention areincluded in the second decoder 104 b.

In the third embodiment of the present invention, during the errorcorrection encoding in the row direction, error correction encoding forthe error-correcting code in the column direction, for which the errorcorrection encoding has been done once, is carried out again. This isnot a hard and fast rule. That is, during the error correction encodingin the column direction, the error correction encoding for theerror-correcting code in the row direction, for which error correctionencoding has been done once, may be carried out again. However, errorcorrection in the row direction occurs when error correction encoding inthe row direction is carried out while error correction encoding in thecolumn direction is taking place. As a result, the error correctionencoding of a higher accuracy can be carried out.

According to the third embodiment of the present invention, theredundant data area E4, in which the error-correcting code obtained byerror correction encoding in the row direction of (n×m) parallel datastream are stored, is added by the second demultiplexer 72. The FECframe generating encoder 73 creates (n×(m+i)) parallel data stream. TheFEC frame bottom decoder 83 decodes, based on the (n×(m+i)) paralleldata stream into (n×m) parallel data stream. The third multiplexer 84multiplexes the (n×m) parallel data stream in n parallel data stream.Fast conversion therefore is achieved with such a simple structure. Inaddition, in the present embodiment, a superior error correctioncapability is achieved as the bit errors that remain uncorrectedfollowing a first error correction are reliably corrected. Hence, anoptical transmission system with high error correction capability and inwhich a transmission of a large amount of signals over long distancescan be achieved.

A fourth embodiment of the present invention is explained next. In thefourth embodiment, similar to the second embodiment, a soft decisiondecoding process has been implemented on the device at the receiver(decoding) end.

FIG. 14 illustrates the overall structure of the optical transmissionsystem according to the fourth embodiment of the present invention. Thisoptical transmission system includes, instead of the second opticalreceiver 5 and the FEC demultiplexer 6 according to the thirdembodiment, a second optical receiver 115 and a FEC demultiplexer 116,respectively. The rest of the structure is identical to that of thethird embodiment and identical parts in the two embodiments are assignedidentical reference numerals. The second optical receiver 115 as well asconverting optical signals received from an optical transmission channel4 into electrical signals, carries out a soft decision process on theelectrical signals, quantizes the binary data into j bits (where j is apositive integer of 2 or greater), and outputs a FEC frame as 3 paralleldata stream of 13 Gbps to the FEC demultiplexer 116. The FECdemultiplexer 116 carries out a soft decision decoding based on the 3parallel data stream.

FIG. 15 is a block diagram of the FEC demultiplexer 116 shown in FIG.14. The FEC demultiplexer 116 includes, instead of the thirddemultiplexer 81, the fourth demultiplexer 82, and the FEC frame bottomdecoder 83 shown in FIG. 11, a third demultiplexer 121, a fourthdemultiplexer 122, and a FEC frame bottom decoder 123, respectively. Therest of the structure is similar to the FEC demultiplexer shown in FIG.11 and identical parts are assigned identical reference numerals.

In FIG. 15, the third demultiplexer 121 demultiplexes j parallel datastream of 12 Gbps received from the second optical receiver 115 into(n×j) parallel data stream and outputs the (n×j) parallel data stream tothe fourth demultiplexer 122. The fourth demultiplexer 122 demultiplexesthe received (n×j) parallel data stream into (n×(m+i)×j) parallel datastream and outputs the (n×(m+i)×j) parallel data stream to the FEC framebottom decoder 123. The FEC frame bottom decoder 123 carries out a softdecision decoding based on the received (n×(m+i)×j) parallel data streamand outputs a decoded (n×m) parallel data stream.

The FEC demultiplexer 116 shown in FIG. 14 is explained next withreference to the detailed block diagram shown in FIG. 16. The FECdemultiplexer 116 includes, instead of the second 1 to 16serial-parallel converter 101, the 1 to 9 serial-parallel converter 102and the decoder 104 of the demultiplexer shown in FIG. 13, a (1 to 16)×3serial-parallel converter 131, a (1 to 9)×3 serial-parallel converter132, and a decoder 134, respectively. The rest of the structure isidentical to the FEC demultiplexer shown in FIG. 3 and identical partsare assigned identical reference numerals.

The (1 to 16)×3 serial-parallel converter 131 multiplexes the received 3data into a 48 (16×3) parallel data stream of 753 Mbps, splits this 48parallel data stream into 3 streams, and outputs each of the 3 paralleldata stream to a corresponding (1 to 9)×3 serial-parallel converter 132place next. There are sixteen (1 to 9)×3 serial-parallel converters 132arranged in a parallel fashion. Each (1 to 9)×3 serial-parallelconverter 132 demultiplexes the 27 ((9×3)) parallel data stream,collectively generates a 432 ((144×3)) of 84 Mbps, and outputs the 432parallel data stream to a frame synchronization circuit 103. The framesynchronization circuit 103 checks the frame synchronization patternfrom the overhead bit, detects the header position of the FEC frame, andoutputs the frame-synchronized 432 parallel data stream to the decoder134.

The decoder 134 carries out the soft decision decoding of the 432parallel data stream of 84 Mbps as 3 quantized 144 parallel data stream,and outputs, a decoded 128 parallel data stream to an overheadseparating circuit 105. The subsequent steps are the same as those inthe third embodiment.

The decoder 134 comprises a first decoder 134 a, which corresponds tothe first decoder 104 a, and a second decoder 134 b, which correspondsto the second decoder 104 b. The first decoder 134 a decodeserror-correcting code in the row direction and outputs, as a result, a 3soft decision value. The second decoder 134 b decodes theerror-correcting code in the column direction and outputs, as a result,a 3 soft decision value. The second decoder 134 then outputs, based onthis soft decision value, the final decoding result. In general, errorcorrection capability improves remarkably with a soft decision decodingas compared to a hard decision decoding. Consequently, by employing asoft decision decoding, an optical transmission system can be achievedwhich can transmit a large amount of signals over long distances. Astructure may be such that the frame synchronization circuit 103 maydetermine frame synchronization either by a 3 soft decision data or by ahard decision data.

To sum up, according to the fourth embodiment, the third demultiplexer121 the j parallel data stream, which is quantized into j bits by thesoft decision process, into the (n×j) parallel data stream. The fourthdemultiplexer 122 demultiplexes the (n×(m+i)×j) parallel data streaminto the (n×m×j) parallel data stream and converts the j data quantizedthe soft decision process into a low rate (n×m) parallel data stream.The FEC frame bottom decoder 123 then carries out the error correctiondecoding. In this way, with a simple structure signals can betransmitted at a high rate. Further, the error correction capability ofsuch a structure is considerably improved with enhanced transmissionrate of a large amount of, signals over long distances.

A fifth embodiment of the present invention is explained next. In thefirst through fourth embodiments BCH codes are used as error-correctingcode in the row direction as well as the column direction. Theerror-correcting codes need not necessarily be only BCH codes. Othererror-correcting codes such as Reed-Solomon codes or, Reed-Muller codesmay also be used. Convolution codes may also be used. However, it ispreferable to use an error-correcting code in which the volume ofredundant bits is fixed, such as in a block code, for maintainingtransmission rate.

Further, the error-correcting code in the row direction and theerror-correcting code in the column direction may be of different types.The error-correcting codes in the two directions may be selected basedon whether the criterion is maintenance of error correction capabilityor rate of transmission or simplicity of the structure.

A sixth embodiment of the present invention is explained next. In thefirst through fourth embodiments, error correction encoding is carriedout both in the row direction and the column direction. That is errorcorrection encoding in the two directions that are mutually orthogonal.However, in the sixth embodiment, the row direction and the columndirections are two different directions which are not mutuallyorthogonal and in which error-correcting codes are generated.

FIG. 17 is a block diagram of a FEC multiplexer according to the sixthembodiment in an optical transmission system. FIG. 18 is a block diagramof a FEC demultiplexer according to the sixth embodiment. The overallstructure of the optical transmission system is identical to the opticaltransmission system shown in FIG. 7. However, the structures of the FECmultiplexer 2 and the FEC demultiplexer 56 are different and areillustrated, respectively, in FIG. 17 and FIG. 18.

The FEC multiplexer shown in FIG. 17 is identical to the FEC multiplexershown in FIG. 2. However, the FEC multiplexer shown in FIG. 17 includes,instead of the second demultiplexer 12 and the FEC frame generatingencoder 13 in FIG. 2, a second demultiplexer 142 and a FEC framegenerating encoder 143, respectively, that are structurally differentfrom their counterparts in FIG. 2. The second demultiplexer 142demultiplexes n parallel data stream received from a first demultiplexer11 into (n×m) parallel data stream and outputs the (n×m) parallel datastream to the FEC frame generating encoder 143. The FEC frame generatingencoder 143, unlike the FEC frame generating encoder 13, carries outerror correction encoding in a diagonal direction and not in the columndirection. However, the FEC frame generating encoder 143 does carry outerror correction encoding in the row direction. As a result, thedirection in which error-correcting codes are generated are notorthogonal. However, as the directions are different, are treated asindependent error-correcting codes during error correction decoding.Consequently, the bit errors are distributed between theerror-correcting codes in the two directions. As a result, the errorcorrection capability in this case is comparable to the error correctioncapability in the case in which code generation takes place in mutuallyorthogonal directions. Besides, as the FEC frame generating encoder 143generates codes in the diagonal direction, there is no need to add anerror-correcting code at the end (bottom) of the column direction.Therefore, an error-correcting code may be added only at the end of therow direction. As a result, the second demultiplexer 142 does not needto add an area corresponding to the redundant data area E5, making thestructure simpler. In this case, the FEC frame generating encoder 143carries out a rate change corresponding to the addition oferror-correcting code in the diagonal direction.

The FEC demultiplexer shown in FIG. 18 is identical to the FECdemultiplexer shown in FIG. 8. However, the FEC demultiplexer shown inFIG. 18 includes, instead of the FEC frame bottom decoder 53 and thethird multiplexer 24 in FIG. 8, a FEC frame bottom decoder 153 and athird multiplexer 154, respectively, that are structurally differentfrom their counterparts in FIG. 8. The FEC frame bottom decoder 153carries out decoding based on the error-correcting code in the rowdirection that are added by the FEC frame generating encoder 143. TheFEC frame bottom decoder 153 then carries out decoding based on theerror-correcting code in the diagonal direction. The subsequent stepsare identical to those of the FEC frame bottom decoder 53. In this case,the FEC frame bottom decoder 153 outputs to a third multiplexer 154 an(n×m) parallel data stream. The third multiplexer 154, like the seconddemultiplexer 142, has a simple structure since it does not need toremove an area corresponding to the redundant data area E5.

FIG. 19( a) and (b) are schematic diagrams that illustrate the errorcorrection encoding process of the FEC frame generating encoder 143shown in FIG. 17. Error correction encoding of the received (n×m)parallel data stream takes places first in the diagonal direction, asshown in FIG. 19( b). The resulting error-correcting code is stored in aredundant data area E15 which is located at the end of the rowdirection. Following this, error correction encoding in the rowdirection, including the redundant data area E15, is carried out. Theresulting error-correcting code is stored in a redundant data area E14which is located after the redundant data area E15. Consequently, theerror-correcting code generated in the row direction, which is at 45°with respect to the diagonal direction, and is independent of theerror-correcting code generated in the diagonal direction.

In the sixth embodiment, error correction encoding is shown to becarried out in a single frame. However, multi-frame error correctionencoding may also be carried out and an error correction encoding forthis error correction encoding may also be carried out.

FIG. 20 illustrates an example of the error correction encoding processin a multi-frame setup. Frames F1 and F2 are considered as a singleframe and error correction encoding is carried out for them in thediagonal direction. The resulting error-correcting code is split andstored in a redundant data area E25 for the frame F1 and a redundantdata area E35 for the frame F2. Following this, error correctionencoding is carried out in the row direction of the frames F1 and F2,which now include the redundant data areas E25 and E35. The resultingerror-correcting codes are stored in a redundant data area E24 for theframe F1 and a redundant data area E34 for the frame F2.

During error correction decoding in this kind of a multi-frame setup,first an error correction decoding is carried out based on theerror-correcting codes in the row direction stored in the redundant dataareas E24 and E34 of the frames F1 and F2, respectively, which alsoincludes redundant data areas E25 and E35. Following this, an errorcorrection decoding is carried out, considering the frames F1 and F2 asa single frame, based on the error-correcting code in the diagonaldirection that is split and stored in the redundant data areas E25 andE35 of the frames F1 and F2, respectively.

According to the sixth embodiment of the present invention,error-correcting code is generated in the diagonal direction as well asthe row direction. The structures of the second demultipelxer 142 andthe third multiplexer 154 are simplified as a combined error correctionencoding is carried out. As a result, high rate transmission with higherror correction capability can be achieved with a simple structure.

A seventh embodiment of the present invention is explained next. In thefirst through sixth embodiment, the FEC frame bottom decoder in thefirst stage carries out error correction decoding using theerror-correcting code in the row direction and then in the second stagecarries out error correction decoding using the error-correcting code inthe column direction or the diagonal direction, as the case may be.However, in the seventh embodiment, error correction decoding is carriedout by repeating plural first and second stages in a continuous manner.

In other words, if a FEC frame generating encoder carries out turboencoding, according to the seventh embodiment of the present invention,the FEC frame bottom decoder carries out decoding of the turbo codes,enhancing the error correction capability. Using a soft decision processcan particularly result in a superior error correction capability.

FIG. 21 is a block diagram of a decoder according to the seventhembodiment of the present invention employed in an optical transmissionsystem. A first decoder 161 outputs to an interleaver 162 a softdecision value obtained by decoding error-correcting code in the rowdirection. A second decoder 163 outputs to a deinterleaver 164 a softdecision value obtained by decoding error-correcting code in the columnor diagonal direction for the data interleaved by the interleaver 162.The deinterleaver 164 outputs the soft decision value to the firstdecoder 161. In this way, the decoding by the first decoder 161 and thesecond decoder 163 is repeated a specified number of times. The finaldecoding result is output from the second decoder. Since the same firstdecoder 161, interleaver 162, second decoder 163, and deinterleaver 164carry out the cycles repeatedly, the structure remains simple.

An eighth embodiment of the present invention is explained next. In thefirst through seventh embodiments dummy bits are added in the fixedstuff area E3. However, in the eighth embodiment overhead bits arestored in a fixed stuff area E3.

In other words, the fixed stuff area E3 is used as an overhead data areaE2. As a result, the amount of data required for maintenance andoperation of an optical transmission system can be further increased.

To sum up, according to the present invention, a demultiplexer receivesand demultiplexes a serial data stream into plural bit parallel datastream. A first encoder carries out error correction encoding in a firstdirection of a matrix constituted by the parallel data stream and adds afirst error-correcting code to the parallel data stream. A secondencoder carries out error correction encoding in a second direction ofthe matrix constituted by the parallel data stream and adds a seconderror-correcting code to the parallel data stream. A multiplexermultiplexes the parallel data stream encoded by the first encoder andthe second encoder and outputs a serial data stream. Theerror-correcting codes in the two directions are independent of eachother because of the serial data stream, and the bit errors aredistributed. Consequently, the transmission rate of the transmissiondata itself is enhanced and besides the increase in the transmissionrate due to the redundant bit. Even if there is deterioration in thetransmission characteristics, error correction capability can beenhanced.

According to the next invention, in the above invention, thedemultiplexer demultiplexes the received serial data stream into nparallel data stream (where n is a positive integer) and demultiplexesthe n parallel data stream further into (n×m) parallel data stream(where m is a positive integer). The first encoder and the secondencoder outputs the received (n×m) parallel data stream as (n×(m+i))parallel data stream (where m and i are positive integers and m isgreater than i) to the multiplexer. The multiplexer multiplexes thereceived (n×(m+i)) parallel data stream into n parallel data stream andoutputs the n parallel data stream as a serial data stream.Consequently, an encoding that is consistent with the error correctionencoding is reliably carried out.

According to the next invention, in the above invention, the firstencoder carries out an error correction encoding in the column directionof the matrix constituted by the parallel data stream and adds theresulting first error-correcting code to the parallel data stream. Thesecond encoder carries out error correction encoding and adds theresulting second error-correcting code to the parallel data stream. Theerror correction encoding by the first encoder is independent of theerror correction encoding by the second encoder. Consequently, anenhanced error correction capability is achieved.

According to the next invention, in the above invention, the firstencoder adds the first error correcting code to a specific row at theend of columns of the parallel data stream and the second encoder addsthe second error correcting code to a specific column at the end of therows of the parallel data stream. Consequently, a soft process can becarried out corresponding to the matrix form of the parallel datastream.

According to the next invention, in the above invention, thedemultiplexer adds to the parallel data stream an area in which thefirst error-correcting code generated by the first encoder is stored.The load on the first encoder and the second encoder is reduced as theareas for storing the error correcting codes are created when there isflexibility during low rate. Besides, areas for error-correcting codesare formed using a simple structure.

According to the next invention, in the above invention, the firstencoder carries out error correction encoding in a diagonal direction ofthe matrix constituted by the parallel data stream and adds theresulting error-correcting code to the parallel data stream. The secondencoder carries out error correction encoding in the row direction ofthe matrix constituted by the parallel data stream and adds theresulting error-correcting code to the parallel data stream. Thedirections of the error correction encoding by the first encoder and thesecond encoder are therefore not orthogonal. Consequently, even if thetwo error-correcting codes are of the same type, independenterror-correcting codes that are soft and multiplexed can be realized.

According to the next invention, in the above invention, the firstencoder adds the first error-correcting code to a specific row at theend of the columns of the parallel data stream. The second encoder addsthe second error-correcting code adjacent to error-correcting code addedby the first encoder. Consequently, soft processing corresponding to thematrix form of the parallel data stream can be carried out.

According to the next invention, in the above invention, the secondencoder carries out error correction encoding for the parallel datastream which includes the first error-correcting code added by the firstencoder and adds the resulting second error-correcting code to theparallel data stream. In this way, the second encoder also corrects theerrors in the error-correcting code generated by the first encoder. As aresult, an enhanced error correction capability is achieved.

According to the next invention, in the above invention, the firsterror-correcting code added by the first encoder and the seconderror-correcting code added by the second encoder differ in their codingsystems. Consequently, a soft error correction multiplexer, suited tothe system in which the error correction multiplexer is implemented, canbe realized.

According to the next invention, in the above invention, the firsterror-correcting code added by the first encoder and the seconderror-correcting code added by the second encoder are block codes.Consequently, the capacity of the error-correcting codes can be fixed.As a result, the structure of the encoders can be kept simple and astable operation of the encoders is achieved.

According to the next invention, in the above invention, the firsterror-correcting code added by the first encoder and the seconderror-correcting code added by the second encoder are calculated in thesame block coding system, and differ in the coding conditions. As aresult, enhanced softness is maintained and the encoding process iscarried out with effectiveness.

According to the next invention, in the above invention, the paralleldata stream includes a data area, an overhead data area in the columndirection that is added to the beginning of the row direction of thedata area, and a fixed stuff area, which absorbs the difference arisingfrom the parallel data stream matrix. Consequently, demultiplexing andmultiplexing are easily carried out.

According to the next invention, in the above invention, the quantity ofthe overhead bits is increased by storing the overhead bits in the fixedstuff area. Consequently, the maintenance and operation of the system inwhich the error correction multiplexer is implemented can be carried outmore reliably without having to increase the transmission capacity.

According to the next invention, in the above invention, a demultiplexerdemultiplexes into parallel data stream a multiplexed serial data streamof plural error-correcting codes generated by error correction encodingin two different directions of a parallel data stream.

A decoder gradually decodes the parallel data stream by the pluralerror-correcting codes and outputs a decoded parallel data stream. Amultiplexer multiplexes the parallel data stream decoded by the decoderand outputs a serial data stream. The decoding is carried out by thedecoder using the independent error-correcting codes. Consequently, thetransmission rate of the transmission data itself can be enhanced.Further, transmission rate can be enhanced by addition of the redundantbits. Besides, even if the transmission characteristic deteriorates, anenhanced error correction capability can be achieved.

According to the next invention, in the above invention, a first opticalreceiver converts received an optical signal into an electrical signals.Any one of the error correction multiplexers according to the presentinvention processes the serial data stream output from the first opticalreceiver. A first optical transmitter converts into an optical signalthe electrical signal output from the error correction multiplexer andtransmits the optical signal to the optical transmission channel. Asecond optical receiver converts the optical signal received from theoptical transmission channel into an electrical signal. Any one of theerror correction demultiplexers according to the present inventionprocesses the electrical signals output from the second opticalreceiver. A second optical transmitter converts the electrical signaloutput from the error correction demultiplexer into an optical signal.Consequently, the transmission rate of the transmission data itself canbe enhanced. Further, transmission rate can be enhanced by addition ofthe redundant bits. Besides, even if the transmission characteristicdeteriorates, an enhanced error correction capability can be achieved.As a result, an optical transmission system that can transmit a largeamount of signals over long distance can be realized.

According to the next invention, in the above invention, in ademultiplexing step, received serial data stream is demultiplexed intoparallel data stream. In a first encoding step, error correctionencoding is carried out in a first direction of the matrix constitutedby the parallel data stream. In a second encoding step, error correctionencoding is carried out in a second direction of the matrix constitutedby the parallel data stream. The resulting first and seconderror-correcting codes are added to the parallel data stream. In amultiplexing step, the parallel data stream, to which the pluralerror-correcting codes are added in the first and second encoding steps,is multiplexed and output as,a serial data stream. Consequently, thetransmission rate of the transmission data itself can be enhanced.Further, transmission rate can be enhanced by addition of the redundantbits. Besides, even if the transmission characteristic deteriorates, anenhanced error correction capability can be achieved.

Although the invention has been described with respect to a specificembodiment for a complete and clear disclosure, the appended claims arenot to be thus limited but are to be construed as embodying allmodifications and alternative constructions that may occur to oneskilled in the art which fairly fall within the basic teaching hereinset forth.

INDUSTRIAL APPLICABILITY

An error correction multiplexer, an error correction demultiplexer, anoptical transmission system employing the error correction multiplexerand the error correction demultiplexer, and an error correctionmultiplexed transmission method according to the present invention issuitable for correction of bit errors caused by deterioration ofsignal-to-noise ratio, based on forward error correction, andimplementing long-haul, high-capacity transmission.

1. An error correction multiplexer comprising: a demultiplexer thatdemultiplexes first serial data stream into parallel data streamconstituting a matrix wherein the matrix includes a data area, anoverload area containing maintenance and operation information, a fixedstuff area which contains overflow data and a row direction redundantarea which contains error correcting code in the column direction and acolumn direction redundant area which contains error correcting code inthe row direction; a first encoder that calculates a first errorcorrecting code from data in a first direction of the matrix, and addsthe first error correcting code to the parallel data stream; a secondencoder that calculates a second error correcting code from data in asecond direction of the matrix, and adds the second error correctingcode to the parallel data stream; and a multiplexer that multiplexes theparallel data stream that is error-correction-coded based on the firsterror correcting code and the second error correcting code into secondserial data stream, and outputs the second serial data stream.
 2. Theerror correction multiplexer according to claim 1, wherein thedemultiplexer demultiplexes the first serial data stream into n paralleldata stream, and demultiplexes the n parallel data stream into n×(m−i)parallel data stream, where n, m, and i are positive integers, and m islarger than i, the first encoder and the second encoder convert then×(m−i) parallel data stream into n×m parallel data stream, and themultiplexer multiplexes the n×m parallel data stream to n parallel datastream, and multiplexes the n parallel data stream into the secondserial data stream.
 3. The error correction multiplexer according toclaim 1, wherein the demultiplexer demultiplexes the first serial datasteam into n parallel data stream, and demultiplexes the n parallel datastream into n×m parallel data stream, where n and m are positiveintegers, the first encoder and the second encoder convert the n×mparallel data stream to n×(m+i) parallel data stream, where i is apositive integer, and m is larger than i, and the multiplexermultiplexes the n×(m+i) parallel data stream to n parallel data stream,and multiplexes the n parallel data stream into the second serial datastream.
 4. The error correction multiplexer according to claim 1,wherein the first direction is column direction of the matrix, and thesecond direction is row direction of the matrix.
 5. The error correctionmultiplexer according to claim 4, wherein the first encoder adds thefirst error correcting code to a predetermined row at an end of thecolumn direction; and the second encoder adds the second errorcorrecting code to a predetermined column at an end of the rowdirection.
 6. The error correction multiplexer according to claim 4,wherein the demultiplexer adds a data area to the parallel data steam,wherein the data area is to be assigned with the first error correctingcode.
 7. The error correction multiplexer according to claim 1, whereinthe first correcting code and the second correcting code differ in codeformat.
 8. The error correction multiplexer according to claim 1,wherein the first correcting code and the second correcting code areblock codes.
 9. The error correction multiplexer according to claim 1,wherein the first correcting code and the second correcting code havesame type of block code format, with different error correction codes.10. The error correction multiplexer according to claim 1, wherein theparallel data stream includes an information area; an overheadinformation area that is added to a top of row direction of theinformation area to form a column of the matrix; and a fixed stuff areato ensure a size of the matrix.
 11. The error correction multiplexeraccording to claim 10, wherein the fixed stuff area stores overheadinformation.
 12. An error correction multiplexer comprising: ademultiplexer that demultiplexes first serial data stream into paralleldata steam constituting a matrix; a first encoder that calculates afirst error correcting code from data in a first direction of thematrix, and adds the first error correcting code to the parallel datastream; a second encoder that calculates a second error correcting codefrom data in a second direction of the matrix, and adds the second errorcorrecting code to the parallel data stream; and a multiplexer thatmultiplexes the parallel data stream that is error-correction-codedbased on the first error correcting code and the second error correctingcode into second serial data steam, and outputs the second serial datastream, wherein the first direction is a diagonal direction of thematrix, and the second direction is a row direction of the matrix. 13.The error correction multiplexer according to claim 12, wherein thefirst encoder adds the first error correcting code to a predeterminedrow at an end of a column direction of the matrix; and the secondencoder adds the second error correcting code to a row adjacent to anend of the row assigned with the first error correcting code.
 14. Theerror correction multiplexer according to claim 12, wherein the secondencoder calculates the second error correcting code from data includingthe first correcting code.
 15. An error correction demultiplexercomprising: a demultiplexer that demultiplexes first serial data streaminto first parallel data stream, wherein the first serial data stream ismultiplexed with a plurality of error correcting codes, and each errorcorrecting code is calculated from data in different direction of amatrix formed by second parallel data stream wherein the matrix includesa data area, an overload area containing maintenance and operationinformation, a fixed stuff area which contains overflow data and a rowdirection redundant area which contains error correcting code in thecolumn direction and a column direction redundant area which containserror correcting code in the row direction; a decoder that decodes thefirst parallel data stream into third parallel data stream based on theerror correcting codes; and a multiplexer that multiplexes the thirdparallel data stream into second serial data stream, and outputs thesecond serial data stream.
 16. The error correction demulfiplexeraccording to claim 15, wherein the demultiplexer demultiplexes the firstserial data stream into n parallel data stream, and demultiplexes the nparallel data stream into n×m parallel data stream, where n and m arepositive integers, the decoder converts the n×m parallel data stream ton×(m−i) parallel data stream, where i is a positive integer, and m islarger than i, and the multiplexer multiplexes the n×(m−i) parallel datastream to n parallel data stream, and multiplexes the n parallel datastream into the second serial data stream.
 17. The error correctiondemultiplexer according to claim 15, wherein the demultiplexerdemultiplexes the first serial data stream into n parallel data stream,and demultiplexes the n parallel data stream into n×(m+i) parallel datastream, where n, m, and i are positive integers, and m is larger than i,the decoder converts the n×(m+i) parallel data stream to n×m paralleldata stream, and the multiplexer multiplexes the n×m parallel datastream to n parallel data stream, and multiplexes the n parallel datastream into the second serial data stream.
 18. The error correctiondemultiplexer according to claim 15, wherein the decoder includes afirst decoder that extracts a first error correcting code from the firstparallel data stream, and applies error correction decoding process todata in a first direction of a matrix formed by the first parallel datastream, wherein the first direction corresponds to the first errorcorrecting code; and a second decoder that extracts a second errorcorrecting code from the first parallel data stream, and applies theerror correction decoding process to data in a second direction of thematrix formed by the first parallel data stream, wherein the seconddirection corresponds to the second error correcting code.
 19. The errorcorrection demultiplexer according to claim 18, wherein the seconddecoder performs the error correction decoding process by using a resultof the decoding by the first decoder.
 20. The error correctiondemultiplexer according to claim 19, wherein the demultiplexerdemultiplexes fourth parallel data stream that is quantized into aplurality of bits by soft decision processing, the first decoder and thesecond decoder decode data by soft decision decoding, and the seconddecoder decode data by using a result of the decoding by the firstdecoder.
 21. The error correction demultiplexer according to claim 19,wherein the demultiplexer demultiplexes fourth parallel data stream thatis quantized into a plurality of bits by soft decision process, thefirst decoder and the second decoder are cascaded to perform softdecision decoding iteratively.
 22. The error correction demultiplexeraccording to claim 19, wherein the second decoder re-inputs results ofthe decoding for predetermined number of times of repetition to thefirst decoder to perform the soft decision decoding iteratively.
 23. Anoptical transmission system comprising: a first optical receiver thatconverts first optical signals into electrical signals to generate firstserial data stream; an error correction multiplexer that includes afirst demultiplexer that demultiplexes the first serial data stream intofirst parallel data stream constituting a matrix wherein the matrixincludes a data area, an overload area containing maintenance andoperation information, a fixed stuff area which contains overflow dataand a row direction redundant area which contains error correcting codein the column direction and a column direction redundant area whichcontains error correcting code in the row direction; a first encoderthat calculates a first error correcting code from data in a firstdirection of the matrix, and adds the first error correcting code to thefirst parallel data stream; a second encoder that calculates a seconderror correcting code from data in a second direction of the matrix, andadds the second error correcting code to the first parallel data stream;and a first multiplexer that multiplexes the first parallel data streamthat is error-correction-coded based on the first error correcting codeand the second error correcting code into second serial data stream, andoutputs the second serial data stream; a first optical transmitter thatconverts the second serial data stream into second optical signals; anoptical transmission line to transmit the second optical signals; asecond optical receiver that converts the second optical signals inputthrough the optical transmission line into electrical signals togenerate third serial data stream; an error correction demultiplexerthat includes a second demultiplexer that demultiplexes the third serialdata stream into second parallel data steam; a decoder that decodes thesecond parallel data stream into third parallel data stream based on theerror correcting codes; and a second multiplexer that multiplexes thethird parallel data stream into fourth serial data stream, and outputsthe fourth serial data stream; and a second optical transmitter thatconverts the fourth serial data stream into third optical signals. 24.The optical transmission system according to claim 23, wherein thesecond optical receiver performs soft decision process.
 25. A method oferror correction multiplexing transmission comprising: demultiplexingfirst serial data stream into first parallel data stream constituting amatrix wherein the matrix includes a data area, an overload areacontaining maintenance and operation information, a fixed stuff areawhich contains overflow data and a row direction redundant area whichcontains error correcting code in the column direction and a columndirection redundant area which contains error correcting code in the rowdirection; calculating a first error correcting code from data in afirst direction of the matrix; adding the first error correcting code tothe first parallel data stream; calculating a second error correctingcode from data in a second direction of the matrix; adding the seconderror correcting code to the first parallel data stream; andmultiplexing the first parallel data stream into second serial datastream.
 26. The method according to claim 25, wherein the demultiplexingincludes demultiplexing the first serial data stream into n paralleldata stream; and demultiplexing the n parallel data stream into n×(m−i)parallel data stream, where n, m, and i are positive integers, and m islarger than i, the calculating and adding include converting the n×(m−i)parallel data stream into n×m parallel data stream, and the multiplexingincludes multiplexing the n×m parallel data stream to n parallel datastream; and multiplexing the n parallel data stream into the secondserial data stream.
 27. The method according to claim 25, wherein thedemultiplexing includes demultiplexing the first serial data stream inton parallel data stream; and demultiplexing the n parallel data streaminto n×m parallel data stream, where n and m are positive integers, thecalculating and adding include converting the n×m parallel data streamto n×(m+i) parallel data stream, where i is a positive integer, and m islarger than i, and the multiplexing includes multiplexing the n×(m+i)parallel data stream to n parallel data stream; and multiplexing the nparallel data stream into the second serial data stream.
 28. The methodaccording to claim 25, wherein the first direction is a column directionof the matrix, and the second direction is a row direction of thematrix.
 29. The method according to claim 28, wherein the adding thefirst error correcting code includes adding the first error correctingcode to a predetermined row at an end of the column direction; and theadding the second error correcting code includes adding the second errorcorrecting code to a predetermined column at an end of the rowdirection.
 30. The method according to claim 25, wherein the firstcorrecting code and the second correcting code differ in code format.31. The method according to claim 25, wherein the first correcting codeand the second correcting code are block codes.
 32. The method accordingto claim 25, wherein the first correcting code and the second correctingcode have same type of block code format, with different errorcorrection codes.
 33. The method according to claim 32, wherein thefirst parallel data stream includes an information area; an overheadinformation area that is added to a top of row direction of theinformation area to form a column of the matrix; and a fixed stuff areato ensure a size of the matrix, and the method further comprisesassigning overhead information in the fixed stuff area.
 34. The methodaccording to claim 25, further comprising demultiplexing the secondserial data stream into second parallel data stream constituting amatrix; extracting a first error correcting code from the secondparallel data stream; decoding data in a third direction of the matrix,wherein the third direction corresponds to the first error correctingcode; extracting a second error correcting code from the second paralleldata stream; and decoding data in a fourth direction of the matrix,wherein the fourth direction corresponds to the second error correctingcode.
 35. The method according to claim 34, wherein the decoding in thefourth direction is performed by using a result of the decoding in thethird direction.
 36. The method according to claim 35, wherein thedemultiplexing includes demultiplexing third parallel data stream thatis quantized into a plurality of bits by soft decision process, thedecoding includes decoding data by soft decision decoding, and thedecoding in the fourth direction is performed by using a result of thedecoding in the third direction.
 37. The method according to claim 35,wherein the demultiplexing includes demultiplexing third parallel datastream that is quantized into a plurality of bits by soft decisionprocess, and the decoding in the fourth direction repeats soft decisiondecoding by using the result of the decoding in the third direction bypredetermined number of times of repetition.
 38. A method of errorcorrection multiplexing transmission comprising: demultiplexing firstserial data stream into first parallel data stream constituting amatrix; calculating a first error correcting code from data in a firstdirection of the matrix: adding the first error correcting code to thefirst parallel data stream; calculating a second error correcting codefrom data in a second direction of the matrix; adding the second errorcorrecting code to the first parallel data stream; and multiplexing thefirst parallel data stream into second serial data stream. wherein thefirst direction is a diagonal direction of the matrix, and the seconddirection is a row direction of the matrix.
 39. The method according toclaim 38, wherein the adding the first error correcting code includesadding the first error correcting code to a predetermined row at an endof a column direction of the matrix, and the adding the second errorcorrecting code includes adding the second error correcting code to arow adjacent to an end of the row assigned with the first errorcorrecting code.
 40. The method according to claim 38, wherein thecalculating the second error correcting code includes calculating thesecond error correcting code from data including the first correctingcode.